723 search results - page 66 / 145 » Heterogeneous behavioral hierarchy for system level designs |
CHI
2005
ACM
14 years 8 months ago
2005
ACM
This paper presents an exploration of user interfaces, persuasive interfaces and feedback techniques in the domain of the sink. Waterbot is a system to inform and motivate behavio...
IISWC
2009
IEEE
14 years 2 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
ISSS
2002
IEEE
14 years 19 days ago
2002
IEEE
Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable...
EUROPAR
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. Parallel program design patterns provide users a new way to get parallel programs without much effort. However, it is always a serious limitation for most existing parall...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...