419 search results - page 5 / 84 » Heuristic design of property maps |
SEMWEB
2005
Springer
14 years 3 months ago
2005
Springer
Abstract. Much data is published on the Web in XML format satisfying schemas, and to make the Semantic Web a reality, such data needs to be interpreted with respect to ontologies. ...
INFOCOM
2009
IEEE
14 years 4 months ago
2009
IEEE
: Given a logical topology and a physical topology , the survivable logical topology design problem in an IP-overWDM optical network is to map the logical links into lightpaths in ...
MEMOCODE
2010
IEEE
13 years 7 months ago
2010
IEEE
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
SAC
2010
ACM
13 years 10 months ago
2010
ACM
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...
ICCAD
1994
IEEE
14 years 1 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...