901 search results - page 28 / 181 » Hiding Communication Latency in Data Parallel Applications |
MICRO
1997
IEEE
13 years 12 months ago
1997
IEEE
As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the e ects of memory access latency. In this paper, we introduce a nov...
PDP
2010
IEEE
14 years 3 days ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
GRID
2006
Springer
13 years 7 months ago
2006
Springer
Monitoring and correlation of streaming data from multiple sources is becoming increasingly important in many application areas. Example applications include automated commodities...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
The processing power and memory capacity of independent and heterogeneous parallel machines can be combined to form a single parallel system that is more powerful than any of its ...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable d...