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» Hierarchical Interconnect Circuit Models
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IVA
2005
Springer
14 years 1 months ago
Hierarchical Motion Controllers for Real-Time Autonomous Virtual Humans
Abstract. Continuous and synchronized whole-body motions are essential for achieving believable autonomous virtual humans in interactive applications. We present a new motion contr...
Marcelo Kallmann, Stacy Marsella
CGF
2008
151views more  CGF 2008»
13 years 7 months ago
Navigation and Exploration of Interconnected Pathways
Visualizing pathways, i. e. models of cellular functional networks, is a challenging task in computer assisted biomedicine. Pathways are represented as large collections of interw...
Marc Streit, Michael Kalkusch, Karl Kashofer, Diet...
ICCD
2006
IEEE
86views Hardware» more  ICCD 2006»
14 years 4 months ago
Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction
— New back-end design for manufacturability rules have brought guarantee rules for interconnect matching. These rules indicate a certain capacitance matching guarantee given spac...
Rasit Onur Topaloglu, Andrew B. Kahng
IPPS
1999
IEEE
13 years 12 months ago
Hardwired-Clusters Partial-Crossbar: A Hierarchical Routing Architecture for Multi-FPGA Systems
Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing archit...
Mohammed A. S. Khalid, Jonathan Rose
ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
14 years 4 months ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...