319 search results - page 12 / 64 » Hierarchical Simulation of a Multiprocessor Architecture |
163
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AHS
2006
IEEE
15 years 12 months ago
2006
IEEE
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
154
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HPCA
2005
IEEE
16 years 6 months ago
2005
IEEE
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
167
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IISWC
2006
IEEE
15 years 12 months ago
2006
IEEE
— As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip res...
151
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ICPPW
1999
IEEE
15 years 10 months ago
1999
IEEE
We present a new multiple ring network for multiprocessors, called the Multistage Ring Network(MRN). The MRN has a 2-level hierarchy of register insertion rings, and its interconn...
170
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ARC
2011
Springer
15 years 26 days ago
2011
Springer
Abstract. In this paper, we take a MIPS-based open-source uniprocessor soft core, Plasma, and extend it to obtain the Beefarm infrastructure for FPGA-based multiprocessor emulation...