319 search results - page 27 / 64 » Hierarchical Simulation of a Multiprocessor Architecture |
ASPLOS
1991
ACM
13 years 11 months ago
1991
ACM
The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory ...
IEEEPACT
2008
IEEE
14 years 2 months ago
2008
IEEE
Communication overheads are one of the fundamental challenges in a multiprocessor system. As the number of processors on a chip increases, communication overheads and the distribu...
ASPLOS
1991
ACM
13 years 11 months ago
1991
ACM
Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coher...
WSC
1997
13 years 9 months ago
1997
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
1 Developing modern integrated and embedded systems require well-designed processes to ensure flexibility and independency. These features are related to exchangeability of hardw...