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» Hierarchical Simulation of a Multiprocessor Architecture
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PDP
2010
IEEE
13 years 11 months ago
Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
Antonio Flores, Juan L. Aragón, Manuel E. A...
DT
2000
88views more  DT 2000»
13 years 7 months ago
Postsilicon Validation Methodology for Microprocessors
f abstraction as applicable to break the problem's complexity, and innovating better techniques to address complexity of new microarchitectural features. Validation techniques...
Hemant G. Rotithor
CGO
2006
IEEE
14 years 1 months ago
Selecting Software Phase Markers with Code Structure Analysis
Most programs are repetitive, where similar behavior can be seen at different execution times. Algorithms have been proposed that automatically group similar portions of a program...
Jeremy Lau, Erez Perelman, Brad Calder
CN
2008
109views more  CN 2008»
13 years 7 months ago
CoCONet: A collision-free container-based core optical network
Electrical-to-optical domain conversions and vice versa (denoted by O/E/O conversions) for each hop in optical core transport networks impose considerable capital and financial ov...
Amin R. Mazloom, Preetam Ghosh, Kalyan Basu, Sajal...
IROS
2009
IEEE
173views Robotics» more  IROS 2009»
14 years 2 months ago
Biologically inspired compliant control of a monopod designed for highly dynamic applications
— In this paper the compliant low level control of a biologically inspired control architecture suited for bipedal dynamic walking robots is presented. It consists of elastic mec...
Sebastian Blank, Thomas Wahl, Tobias Luksch, Karst...