59 search results - page 9 / 12 » Hierarchical Test Generation with Built-In Fault Diagnosis |
MTV
2005
IEEE
14 years 1 months ago
2005
IEEE
Microprocessor technology is increasingly used for many applications; the large market volumes call for cost containment in the production phase. Process yield for processor produ...
FLAIRS
2006
13 years 9 months ago
2006
Diagnosing multiple faults for a complex system is often very difficult. It requires not only a model which adequately represents the diagnostic aspect of a complex system, but al...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
ICCAD
2000
IEEE
13 years 12 months ago
2000
IEEE
We present an error catch and analysis (ECA) system for semiconductor memories. The system consists of a test algorithm generator called TAGS, a fault simulator called RAMSES, and...