57 search results - page 8 / 12 » Hierarchical Traces for Reduced NSM Memory Requirements |
SAMOS
2005
Springer
14 years 28 days ago
2005
Springer
An analytical performance model for out of order issue superscalar micro-processors is presented. This model quantifies the performance impacts of micro-architecture design option...
OSDI
1994
ACM
13 years 8 months ago
1994
ACM
Mobile computers such as notebooks, subnotebooks, and palmtops require low weight, low power consumption, and good interactive performance. These requirements impose many challeng...
PERVASIVE
2010
Springer
13 years 9 months ago
2010
Springer
We present the design and evaluation of Panoramic, a tool that enables end-users to specify and verify an important family of complex location events. Our approach aims to reduce o...
ISCA
2010
IEEE
13 years 9 months ago
2010
IEEE
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...