Sciweavers

1671 search results - page 329 / 335
» Hierarchical graph maps
Sort
View
VLSID
2000
IEEE
90views VLSI» more  VLSID 2000»
14 years 1 months ago
Performance Analysis of Systems with Multi-Channel Communication Architectures
This paper presents a novel system performance analysis technique to support the design of custom communication architectures for System-on-Chip ICs. Our technique fills a gap in...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
DATE
1999
IEEE
194views Hardware» more  DATE 1999»
14 years 1 months ago
CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems
Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-tim...
Bharat P. Dav
IPPS
1999
IEEE
14 years 1 months ago
Process Networks as a High-Level Notation for Metacomputing
Abstract. Our work involves the development of a prototype Geographical Information System GIS as an example of the use of process networks as a well-de ned high-level semantic mod...
Darren Webb, Andrew L. Wendelborn, Kevin Maciunas
FCCM
1997
IEEE
199views VLSI» more  FCCM 1997»
14 years 1 months ago
The RAW benchmark suite: computation structures for general purpose computing
The RAW benchmark suite consists of twelve programs designed to facilitate comparing, validating, and improving reconfigurable computing systems. These benchmarks run the gamut o...
Jonathan Babb, Matthew Frank, Victor Lee, Elliot W...
ICLP
1997
Springer
14 years 29 days ago
Automatic Termination Analysis of Logic Programs
Abstract This paper describes a general framework for automatic termination analysis of logic programs, where we understand by termination" the niteness of the LD-tree constru...
Naomi Lindenstrauss, Yehoshua Sagiv