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ISLPED
1999
ACM
143views Hardware» more  ISLPED 1999»
14 years 1 months ago
Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
Kanad Ghose, Milind B. Kamble
FOCS
1999
IEEE
14 years 1 months ago
PSPACE Has Constant-Round Quantum Interactive Proof Systems
In this paper we introduce quantum interactive proof systems, which are interactive proof systems in which the prover and verifier may perform quantum computations and exchange qu...
John Watrous
ICPPW
1999
IEEE
14 years 1 months ago
Multistage Ring Network: A New Multiple Ring Network for Large Scale Multiprocessors
We present a new multiple ring network for multiprocessors, called the Multistage Ring Network(MRN). The MRN has a 2-level hierarchy of register insertion rings, and its interconn...
Dongho Yoo, Inbum Jung, Seung Ryoul Maeng, Hyungla...
AGENTS
1999
Springer
14 years 1 months ago
Where to Look? Automating Attending Behaviors of Virtual Human Characters
This research proposes a computational framework for generating visual attending behavior in an embodied simulated human agent. Such behaviors directly control eye and head motion...
Sonu Chopra-Khullar, Norman I. Badler
GD
1999
Springer
14 years 1 months ago
Planarity-Preserving Clustering and Embedding for Large Planar Graphs
In this paper we present a novel approach for cluster-based drawing of large planar graphs that maintains planarity. Our technique works for arbitrary planar graphs and produces a ...
Christian A. Duncan, Michael T. Goodrich, Stephen ...