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ERSA
2009
129views Hardware» more  ERSA 2009»
13 years 5 months ago
Data path Configuration Time Reduction for Run-time Reconfigurable Systems
- The FPGA (re)configuration is a time-consuming process and a bottleneck in FPGA-based Run-Time Reconfigurable (RTR) systems. In this paper, we present a High Level Synthesis (HLS...
Mahmood Fazlali, Ali Zakerolhosseini, Mojtaba Sabe...
BMCBI
2010
124views more  BMCBI 2010»
13 years 7 months ago
A Dynamic Noise Level Algorithm for Spectral Screening of Peptide MS/MS Spectra
Background: High-throughput shotgun proteomics data contain a significant number of spectra from non-peptide ions or spectra of too poor quality to obtain highly confident peptide...
Hua Xu, Michael A. Freitas
BMCBI
2010
97views more  BMCBI 2010»
13 years 5 months ago
Preprocessing of gene expression data by optimally robust estimators
Background: The preprocessing of gene expression data obtained from several platforms routinely includes the aggregation of multiple raw signal intensities to one expression value...
Matthias Kohl, Hans-Peter Deigner
ERSHOV
2006
Springer
13 years 11 months ago
Streaming Networks for Coordinating Data-Parallel Programs
A new coordination language for distributed data-parallel programs is presented, call SNet. The intention of SNet is to introduce advanced structuring techniques into a coordinatio...
Clemens Grelck, Sven-Bodo Scholz, Alexander V. Sha...
IPPS
2006
IEEE
14 years 1 months ago
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based System on Chip (SoC) that meet the applications requirements. The designer can cust...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...