28 search results - page 3 / 6 » High Level Synthesis Of Multi-Precision Data Flow Graphs |
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
Implementing real-time video processing systems put high requirements on computation and memory performance. FPGAs have proven to be effective implementation architecture for thes...
ISSS
2000
IEEE
13 years 11 months ago
2000
IEEE
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
ARCS
2008
Springer
13 years 9 months ago
2008
Springer
Due to increasing complexity of modern real-time image processing applications, classical hardware development at register transfer level becomes more and more the bottleneck of te...
ISLPED
1995
ACM
13 years 10 months ago
1995
ACM
ABSTRACT { Sub-micron technologies and the increasing size and complexity of integrated components have aggravated the e ect of long interconnects and buses, compared to that of ga...