12 search results - page 1 / 3 » High Level Synthesis Techniques for Efficient Built-In-Self ... |
DFT
1993
IEEE
14 years 3 months ago
1993
IEEE
VLSID
2009
IEEE
14 years 11 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
EVOW
2001
Springer
14 years 3 months ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
CCL
1994
Springer
14 years 3 months ago
1994
Springer
Abstract: This paper describes the application of CLP (constraint logic programming) to several digital circuit design problems. It is shown that logic programming together with ef...
DAC
2000
ACM
14 years 12 months ago
2000
ACM
eously demand shorter and less costly design cycles. Designing at higher levels of abstraction makes both objectives achievable, but enabling techniques like behavioral synthesis h...