83 search results - page 16 / 17 » High Level Synthesis for Data-Driven Applications |
FCCM
2011
IEEE
12 years 11 months ago
2011
IEEE
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Code optimization and high level synthesis can be posed as constraint satisfaction and optimization problems, such as graph coloring used in register allocation. Graph coloring is...
IJVR
2006
13 years 7 months ago
2006
In this paper, we will present an overview of existing research in the vast area of IVH systems. We will also present our ongoing work on improving the expressive capabilities of I...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
Milenko Drinic UCLA Computer Science Dep. 4732 Boelter Hall Los Angeles, CA 90095-1596 milenko@cs.ucla.edu Darko Kirovski Microsoft Research One Microsoft Way Redmond, WA 98052 da...
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
Industry’s demand for flexible embedded solutions providing high performance and short time-to-market has led to the development of configurable and extensible processors. The...