31 search results - page 4 / 7 » High Level Synthesis of Pipelined Instruction Set Processors... |
ISCC
2009
IEEE
14 years 2 months ago
2009
IEEE
Reconfigurable computing is one of the most recent research topics in computer science. The Altera™ Nios II soft-core processor can be included in a large set of reconfigurable ...
RSP
2000
IEEE
13 years 12 months ago
2000
IEEE
This paper describes a methodology for developing processor specific tools such as assemblers, disassemblers, processor simulators, compilers etc., using processor models in a ge...
ISPASS
2006
IEEE
14 years 1 months ago
2006
IEEE
The latest high-performance IBM PowerPC microprocessor, the POWER5 chip, poses challenges for performance model validation. The current stateof-the-art is to use simple hand-coded...
SC
1992
ACM
13 years 11 months ago
1992
ACM
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
Branch prediction has enabled microprocessors to increase instruction level parallelism (ILP) by allowing programs to speculatively execute beyond control boundaries. Although spe...