249 search results - page 17 / 50 » High Level Synthesis of Timed Asynchronous Circuits |
ICCAD
2000
IEEE
14 years 2 days ago
2000
IEEE
A tool is presented that gives a high-level estimation of the power consumed by an analog continuous-time OTA-C filter when given only high-level input parameters such as dynamic ...
GECCO
2000
Springer
13 years 11 months ago
2000
Springer
This paper presents a novel evolvable hardware framework for the automated design of digital circuits for high performance applications. The technique evolves circuits correspondi...
ACSD
2003
IEEE
14 years 29 days ago
2003
IEEE
Signal Transition Graphs (STGs) are one of the most popular models for the specification of asynchronous circuits. A STG can be implemented if it admits a so-called consistent an...
CHES
2006
Springer
13 years 11 months ago
2006
Springer
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
ICCAD
2000
IEEE
14 years 2 days ago
2000
IEEE
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...