249 search results - page 31 / 50 » High Level Synthesis of Timed Asynchronous Circuits |
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
ISMVL
2002
IEEE
14 years 18 days ago
2002
IEEE
An impact of introducing multi-level signals to a bandpass delta-sigma modulator (DSM), which is of particular interest for wireless communications applications, has been investig...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
— This paper presents a multiple-voltage high-level synthesis methodology for low power DSP applications using algorithmic transformation techniques. Our approach is motivated by...
FPL
2009
Springer
13 years 11 months ago
2009
Springer
Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a software-like...
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
In this paper we describe, a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire del...