249 search results - page 42 / 50 » High Level Synthesis of Timed Asynchronous Circuits |
VLSID
1999
IEEE
13 years 12 months ago
1999
IEEE
Formal approaches to HW and system design have not been generally adopted, because designers often view the modelling concepts in these approaches as unsuitable for their problems...
DFT
1999
IEEE
13 years 12 months ago
1999
IEEE
The inherent redundancy and in-the-field reconfiguration capabilities of field programmable gate arrays (FPGAs) provide alternatives to integrated circuit redundancy-based fault r...
INFOCOM
1997
IEEE
13 years 12 months ago
1997
IEEE
Due to the increasing reliance of our society on the timely and reliable transfer of large quantities of information (suchas voice, data, and video)across high speed communication...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
ISCAS
2008
IEEE
14 years 2 months ago
2008
IEEE
— It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partiti...