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» High Level Synthesis of Timed Asynchronous Circuits
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SLIP
2004
ACM
14 years 1 months ago
Interconnect-power dissipation in a microprocessor
Interconnect power is dynamic power dissipation due to switching of interconnection capacitances. This paper describes the characterization of interconnect power in a state-of-the...
Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum ...
AICCSA
2008
IEEE
209views Hardware» more  AICCSA 2008»
13 years 9 months ago
Transistor-level based defect tolerance for reliable nanoelectronics
Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant ...
Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Mel...
JCNS
2010
121views more  JCNS 2010»
13 years 2 months ago
Pattern orthogonalization via channel decorrelation by adaptive networks
The early processing of sensory information by neuronal circuits often includes a reshaping of activity patterns that may facilitate the further processing of stimulus representat...
Stuart D. Wick, Martin T. Wiechert, Rainer W. Frie...
DAC
1997
ACM
13 years 12 months ago
Multilevel Hypergraph Partitioning: Application in VLSI Domain
In this paper, we present a new hypergraph partitioning algorithm that is based on the multilevel paradigm. In the multilevel paradigm, a sequence of successively coarser hypergra...
George Karypis, Rajat Aggarwal, Vipin Kumar, Shash...
VTC
2007
IEEE
14 years 1 months ago
Discrete Power Allocation for Lifetime Maximization in Cooperative Networks
Abstract— Discrete power allocation strategies for amplifyand-forward cooperative networks are proposed based on selective relaying methods. The goal of power allocation is to ma...
Wan-Jen Huang, Yao-Win Hong, C. C. Jay Kuo