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MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
15 years 7 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
163
Voted
PIMRC
2010
IEEE
15 years 14 days ago
Improving link failure detection and response in IEEE 802.11 wireless ad hoc networks
Wireless multihop ad hoc networks face a multitude of challenging problems including highly dynamic multihop topologies, lossy and noisy communications channels, and sporadic conne...
Alvin C. Valera, Hwee-Pink Tan, Winston Khoon Guan...
123
Voted
AFRICACRYPT
2009
Springer
15 years 12 days ago
Efficient Acceleration of Asymmetric Cryptography on Graphics Hardware
Graphics processing units (GPU) are increasingly being used for general purpose computing. We present implementations of large integer modular exponentiation, the core of public-ke...
Owen Harrison, John Waldron

Publication
124views
17 years 1 months ago
Survivability in IP over WDM networks
The Internet is emerging as the new universal telecommunication medium. IP over WDM has been envisioned as one of the most attractive architectures for the new Internet. Consequent...
Kulathumani Vinodkrishnan, Nikhil Chandhok, Arjan ...
VLSID
2003
IEEE
147views VLSI» more  VLSID 2003»
16 years 2 months ago
SoC Synthesis with Automatic Hardware Software Interface Generation
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, B...