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ICCD
2003
IEEE
134views Hardware» more  ICCD 2003»
14 years 7 months ago
An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk
Analyzing the effect of crosstalk on delay is critical for high performance circuits. The major bottleneck in performing crosstalkinduced delay analysis is the high computational ...
Venkatesan Rajappan, Sachin S. Sapatnekar
IPTPS
2003
Springer
14 years 3 months ago
Controlling the Cost of Reliability in Peer-to-Peer Overlays
Abstract—Structured peer-to-peer overlay networks provide a useful substrate for building distributed applications but there are general concerns over the cost of maintaining the...
Ratul Mahajan, Miguel Castro, Antony I. T. Rowstro...
ARC
2010
Springer
387views Hardware» more  ARC 2010»
14 years 5 months ago
Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods
Computing the solution to a system of linear equations is a fundamental problem in scientific computing, and its acceleration has drawn wide interest in the FPGA community [1–3]...
David Boland, George A. Constantinides
PVLDB
2010
119views more  PVLDB 2010»
13 years 8 months ago
An Architecture for Parallel Topic Models
This paper describes a high performance sampling architecture for inference of latent topic models on a cluster of workstations. Our system is faster than previous work by over an...
Alexander J. Smola, Shravan Narayanamurthy
IPPS
2006
IEEE
14 years 4 months ago
Parallel FPGA-based all-pairs shortest-paths in a directed graph
With rapid advances in VLSI technology, Field Programmable Gate Arrays (FPGAs) are receiving the attention of the Parallel and High Performance Computing community. In this paper,...
Uday Bondhugula, Ananth Devulapalli, Joseph Fernan...