174 search results - page 22 / 35 » High Performance FPGA Implementation of the Mersenne Twister |
ISPAN
2005
IEEE
14 years 1 months ago
2005
IEEE
Within the parallel computing domain, field programmable gate arrays (FPGA) are no longer restricted to their traditional role as substitutes for application-specific integrated...
FPL
2009
Springer
13 years 10 months ago
2009
Springer
The acceleration of molecular dynamics (MD) simulations using high performance reconfigurable computing (HPRC) has been much studied. Given the intense competition from multicore...
INFOCOM
2006
IEEE
14 years 1 months ago
2006
IEEE
— A key function for network traffic monitoring and analysis is the ability to perform aggregate queries over multiple data streams. Change detection is an important primitive w...
ASPLOS
2011
ACM
12 years 11 months ago
2011
ACM
The adoption of transactional memory is hindered by the high overhead of software transactional memory and the intrusive design changes required by previously proposed TM hardware...
ARC
2009
Springer
14 years 4 days ago
2009
Springer
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...