174 search results - page 4 / 35 » High Performance FPGA Implementation of the Mersenne Twister |
FCCM
2011
IEEE
12 years 11 months ago
2011
IEEE
Abstract—Ballooning traffic volumes and increasing linkspeeds require ever high compute power to perform complex real-time processing of network packets. FPGAs have already been...
ARC
2012
Springer
12 years 3 months ago
2012
Springer
Iterative numerical algorithms with high memory bandwidth requirements but medium-size data sets (matrix size ∼ a few 100s) are highly appropriate for FPGA acceleration. This pap...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the conf...
DSD
2009
IEEE
13 years 11 months ago
2009
IEEE
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computat...
FPL
2006
Springer
13 years 11 months ago
2006
Springer
A field-programmable gate array (FPGA) implementation of a new detection algorithm for uncoded multiple inputmultiple output (MIMO) systems based on the complex version of the sph...