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» High Performance Matrix Multiplication on Many Cores
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ISCA
2008
IEEE
113views Hardware» more  ISCA 2008»
14 years 3 months ago
A Two-Level Load/Store Queue Based on Execution Locality
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
Miquel Pericàs, Adrián Cristal, Fran...
CHI
2006
ACM
14 years 9 months ago
Generating automated predictions of behavior strategically adapted to specific performance objectives
It has been well established in Cognitive Psychology that humans are able to strategically adapt performance, even highly skilled performance, to meet explicit task goals such as ...
Katherine Eng, Richard L. Lewis, Irene Tollinger, ...
GLOBECOM
2009
IEEE
14 years 3 months ago
From Trees to DAGs: Improving the Performance of Bridged Ethernet Networks
—Ethernet is widely used in Local Area Networks (LANs) due to its simplicity and cost effectiveness. Today, a great deal of effort is being devoted to extending Ethernet capabili...
Chen Avin, Ran Giladi, Nissan Lev-Tov, Zvi Lotker
HPCA
2007
IEEE
14 years 9 months ago
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications
Chip multiprocessors with multiple simpler cores are gaining popularity because they have the potential to drive future performance gains without exacerbating the problems of powe...
Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlk...
PVLDB
2010
179views more  PVLDB 2010»
13 years 7 months ago
MRShare: Sharing Across Multiple Queries in MapReduce
Large-scale data analysis lies in the core of modern enterprises and scientific research. With the emergence of cloud computing, the use of an analytical query processing infrast...
Tomasz Nykiel, Michalis Potamias, Chaitanya Mishra...