142 search results - page 14 / 29 » High Performance Pipelined Process Migration with RDMA |
DSN
2008
IEEE
14 years 2 months ago
2008
IEEE
Many emerging distributed applications require the realtime processing of large amounts of data that are being updated continuously. Distributed stream processing systems offer a ...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
This short paper explores an implementation of a new technology called 3D die stacking and describes research activity at Intel. 3D die stacking is the bonding of two die either f...
DICS
2006
13 years 11 months ago
2006
Virtual laboratories can be characterized by their long-lasting, large-scale computations, where a collection of heterogeneous tools is integrated into data processing pipelines. S...
ASYNC
2003
IEEE
14 years 25 days ago
2003
IEEE
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...
ISCA
2010
IEEE
14 years 19 days ago
2010
IEEE
As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations...