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ISSS
1995
IEEE
115views Hardware» more  ISSS 1995»
13 years 11 months ago
A system level design methodology for the optimization of heterogeneous multiprocessors
This paper presents a system level design methodology and its implementation as CAD tool for the optimization of heterogeneous multiprocessor systems. These heterogeneous systems,...
Markus Schwiegershausen, Peter Pirsch
ICPPW
1999
IEEE
13 years 12 months ago
Multistage Ring Network: A New Multiple Ring Network for Large Scale Multiprocessors
We present a new multiple ring network for multiprocessors, called the Multistage Ring Network(MRN). The MRN has a 2-level hierarchy of register insertion rings, and its interconn...
Dongho Yoo, Inbum Jung, Seung Ryoul Maeng, Hyungla...
MICRO
2000
IEEE
95views Hardware» more  MICRO 2000»
13 years 7 months ago
A Single-Chip Multiprocessor for Smart Terminals
dards, language abstraction continues unabatrpretation of such high-level abstract languages requires high performance. The MP98 low-power, high-performance microprocessor architec...
Masato Edahiro, Satoshi Matsushita, Masakazu Yamas...
TJS
2010
145views more  TJS 2010»
13 years 2 months ago
Analyzing and enhancing the parallel sort operation on multithreaded architectures
The Sort operation is a core part of many critical applications. Despite the large efforts to parallelize it, the fact that it suffers from high data-dependencies vastly limits it...
Layali K. Rashid, Wessam Hassanein, Moustafa A. Ha...
CF
2009
ACM
14 years 6 days ago
Non-clairvoyant speed scaling for batched parallel jobs on multiprocessors
Energy consumption and heat dissipation have become key considerations for modern high performance computer systems. In this paper, we focus on non-clairvoyant speed scaling to mi...
Hongyang Sun, Yangjie Cao, Wen-Jing Hsu