80 search results - page 6 / 16 » High level synthesis for reconfigurable datapath structures |
DAC
2006
ACM
14 years 9 months ago
2006
ACM
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
DSD
2010
IEEE
13 years 6 months ago
2010
IEEE
Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible natur...
VLSID
1994
IEEE
14 years 2 days ago
1994
IEEE
In this paper, we present a formal analysis of the constraints of the scheduling problem, and evaluate the structure of the scheduling polytope described by those constraints. Pol...
ARC
2008
Springer
13 years 10 months ago
2008
Springer
We present an improved method for scheduling speculative data paths which relies on cancel tokens to undo computations in misspeculated paths. Performancewise, this method is consi...
AAAI
2007
13 years 10 months ago
2007
The gap in automation between MIP/SAT solvers and those for constraint programming and constraint-based local search hinders experimentation and adoption of these technologies and...