18572 search results - page 15 / 3715 » High performance C |
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
– Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based com...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
PPSC
1997
13 years 9 months ago
1997
We illustrate how Fortran 90 supports object-oriented concepts by example of plasma particle computations on the IBM SP. Our experience shows that Fortran 90 and object-oriented m...
ICASSP
2011
IEEE
12 years 11 months ago
2011
IEEE
Recognizer Output Voting Error Reduction (ROVER), is a well-known procedure for decoders’ combination aiming at reducing the Word Error Rate (WER) in transcription applications....
SIGPLAN
1998
13 years 7 months ago
1998
A high performance implementation of C++ exception handling is crucial, because exception handling overhead is distributed across all code. The commonly-used table-driven approach...