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TCAD
2010
105views more  TCAD 2010»
13 years 4 months ago
Fault Tolerant Network on Chip Switching With Graceful Performance Degradation
The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity eve...
Adán Kohler, Gert Schley, Martin Radetzki
IAT
2010
IEEE
13 years 7 months ago
An Agent Model for Analysis of Human Performance Quality
-- A human's performance in a complex task is highly dependent on the demands of the task, in the sense that highly demanding situations will often cause a degradation of perf...
Michel C. A. Klein, Rianne van Lambalgen, Jan Treu...
INFOCOM
2007
IEEE
14 years 4 months ago
Congestion Control for Small Buffer High Speed Networks
— There is growing interest in designing high speed routers with small buffers that store only tens of packets. Recent studies suggest that TCP NewReno, with the addition of a pa...
Yu Gu, Donald F. Towsley, C. V. Hollot, Honggang Z...
ANNS
2007
13 years 11 months ago
Direct and indirect classification of high-frequency LNA performance using machine learning techniques
The task of determining low noise amplifier (LNA) high-frequency performance in functional testing is as challenging as designing the circuit itself due to the difficulties associa...
Peter C. Hung, Seán F. McLoone, Magdalena S...
DATE
2004
IEEE
152views Hardware» more  DATE 2004»
14 years 1 months ago
A Design Methodology for the Exploitation of High Level Communication Synthesis
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
Francesco Bruschi, Massimo Bombana