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PDP
2010
IEEE
14 years 1 months ago
Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
Antonio Flores, Juan L. Aragón, Manuel E. A...
PPOPP
2009
ACM
14 years 9 months ago
An efficient transactional memory algorithm for computing minimum spanning forest of sparse graphs
Due to power wall, memory wall, and ILP wall, we are facing the end of ever increasing single-threaded performance. For this reason, multicore and manycore processors are arising ...
Seunghwa Kang, David A. Bader
TC
2010
13 years 7 months ago
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment
—The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially ...
Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pr...
IROS
2009
IEEE
162views Robotics» more  IROS 2009»
14 years 3 months ago
Novel mechanical design of biped robot SHERPA using 2 DOF cable differential modular joints
— This paper discusses the mechanical kinematics solutions and design aspects of the biped robot SHERPA, a bipedal platform able to walk and carry load. Starting from the analysi...
Ionut Mihai Constantin Olaru, Sébastien Kru...
ICDCS
2002
IEEE
14 years 1 months ago
Accelerating Internet Streaming Media Delivery using Network-Aware Partial Caching
Internet streaming applications are affected by adverse network conditions such as high packet loss rates and long delays. This paper aims at mitigating such effects by leveraging...
Shudong Jin, Azer Bestavros, Arun Iyengar