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IEEEPACT
2005
IEEE
14 years 2 months ago
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
Huiyang Zhou
ICS
2009
Tsinghua U.
14 years 3 months ago
Towards 100 gbit/s ethernet: multicore-based parallel communication protocol design
Ethernet line rates are projected to reach 100 Gbits/s by as soon as 2010. While in principle suitable for high performance clustered and parallel applications, Ethernet requires ...
Stavros Passas, Kostas Magoutis, Angelos Bilas
FCCM
2006
IEEE
170views VLSI» more  FCCM 2006»
14 years 18 days ago
An Architecture for Efficient Hardware Data Mining using Reconfigurable Computing Systems
The Apriori algorithm is a fundamental correlation-based data mining kernel used in a variety of fields. The innovation in this paper is a highly parallel custom architecture impl...
Zachary K. Baker, Viktor K. Prasanna
EUROPAR
1999
Springer
14 years 1 months ago
Consequences of Modern Hardware Design for Numerical Simulations and Their Realization in FEAST
This paper deals with the influence of hardware aspects of modern computer architectures to the design of software for numerical simulations. We present performance tests for vari...
Christian Becker, Susanne Kilian, Stefan Turek
SP
2008
IEEE
122views Security Privacy» more  SP 2008»
13 years 8 months ago
Large-scale phylogenetic analysis on current HPC architectures
Abstract. Phylogenetic inference is considered a grand challenge in Bioinformatics due to its immense computational requirements. The increasing popularity and availability of larg...
Michael Ott, Jaroslaw Zola, Srinivas Aluru, Andrew...