733 search results - page 89 / 147 » High performance in tree-based parallel architectures |
ICASSP
2008
IEEE
14 years 3 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
IPPS
2007
IEEE
14 years 3 months ago
2007
IEEE
This paper investigates the utilization of the master-slave (MS) paradigm as an alternative to domain decomposition (DD) methods for parallelizing lattice gauge theory (LGT) model...
ARITH
2007
IEEE
14 years 3 months ago
2007
IEEE
We describe a new method to perform the modular exponentiation operation, i.e., the computation of c = me mod n, where c, m, e and n are large integers. The new method uses the di...
EUROPAR
2009
Springer
14 years 1 months ago
2009
Springer
Abstract. We investigate the performance of two approaches for matrix inversion based on Gaussian (LU factorization) and Gauss-Jordan eliminations. The target architecture is a cur...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
Focused around the field of the exploitation and the administration of high performance large-scale parallel systems , this article describes the work carried out on the deployme...