733 search results - page 92 / 147 » High performance in tree-based parallel architectures |
HPCA
1997
IEEE
14 years 1 months ago
1997
IEEE
This paper represents a design study of the datapath for a very long instruction word (VLIW) video signal processor (VSP). VLIW architectures provide high parallelism and excellen...
ICPPW
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract— Most image processing applications are characterized by computation-intensive operations, and high memory and performance requirements. Parallelized implementation on s...
ICCD
2004
IEEE
14 years 5 months ago
2004
IEEE
A programmable parallel digital signal processor (DSP) core for embedded applications is presented which combines the concepts of single instruction stream over multiple data stre...
CCGRID
2008
IEEE
14 years 3 months ago
2008
IEEE
To be competitive, Enterprises are collecting and analyzing increasingly large amount of data in order to derive business insights. However, there are at least two challenges to m...
CATA
2004
13 years 10 months ago
2004
This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is co...