1024 search results - page 29 / 205 » High-Level Execution Time Analysis |
103
Voted
DEXAW
2008
IEEE
15 years 9 months ago
2008
IEEE
This paper proposes an optimistic concurrency control (CC) algorithm, called Sequential Order with Dynamic Adjustment (SODA), that guarantees timely and correct execution of concu...
136
Voted
DATE
1999
IEEE
15 years 7 months ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
114
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CC
1999
Springer
15 years 7 months ago
1999
Springer
Abstract. Optimizing compilers typically limit the scope of their analyses and optimizations to individual modules. This has two drawbacks: rst, library code cannot be optimized to...
138
Voted
ISORC
2005
IEEE
15 years 8 months ago
2005
IEEE
As complexity of real-time embedded software grows, it is desirable to use formal verification techniques to achieve a high level of assurance. We discuss application of model-ch...
143
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RTAS
2010
IEEE
15 years 1 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...