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CHARME
2005
Springer
119views Hardware» more  CHARME 2005»
14 years 4 months ago
High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design
Petr Matousek, Ales Smrcka, Tomás Vojnar
DSD
2010
IEEE
221views Hardware» more  DSD 2010»
13 years 9 months ago
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis
Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible natur...
Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jea...
ISQED
2003
IEEE
113views Hardware» more  ISQED 2003»
14 years 4 months ago
Using Integer Equations for High Level Formal Verification Property Checking
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
Bijan Alizadeh, Mohammad Reza Kakoee
FMAM
2010
157views Formal Methods» more  FMAM 2010»
13 years 9 months ago
An Experience on Formal Analysis of a High-Level Graphical SOA Design
: In this paper, we present the experience gained with the participation in a case study in which a novel high-level design language (UML4SOA) was used to produce a service-oriente...
Maurice H. ter Beek, Franco Mazzanti, Aldi Sulova
RTSS
1999
IEEE
14 years 3 months ago
High-Level Modeling and Analysis of TCAS
In this paper, we demonstrate a high-level approach to modeling and analyzing complex safety-critical systems through a case study in the area of air traffic management. In partic...
Carolos Livadas, John Lygeros, Nancy A. Lynch