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» High-Performance Extendable Instruction Set Computing
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COLING
2000
13 years 11 months ago
Taking Account of the User's View in 3D Multimodal Instruction Dialogue
While recent advancements in virtual reality technology have created a rich communication interface linking humans and computers, there has been little work on building dialogue s...
Yukiko I. Nakano, Kenji Imamura, Hisashi Ohara
ALIFE
1999
13 years 9 months ago
An Approach to Biological Computation: Unicellular Core-Memory Creatures Evolved Using Genetic Algorithms
A novel machine language genetic programming system that uses one-dimensional core memories is proposed and simulated. The core is compared to a biochemical reaction space, and in ...
Hikeaki Suzuki
ICS
2005
Tsinghua U.
14 years 3 months ago
Reducing latencies of pipelined cache accesses through set prediction
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
Aneesh Aggarwal
PPOPP
2010
ACM
14 years 7 months ago
Data transformations enabling loop vectorization on multithreaded data parallel architectures
Loop vectorization, a key feature exploited to obtain high performance on Single Instruction Multiple Data (SIMD) vector architectures, is significantly hindered by irregular memo...
Byunghyun Jang, Perhaad Mistry, Dana Schaa, Rodrig...
HPCA
2007
IEEE
14 years 10 months ago
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications
Chip multiprocessors with multiple simpler cores are gaining popularity because they have the potential to drive future performance gains without exacerbating the problems of powe...
Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlk...