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» High-Radix Implementation of IEEE Floating-Point Addition
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ASAP
2004
IEEE
140views Hardware» more  ASAP 2004»
14 years 1 months ago
Decimal Floating-Point Division Using Newton-Raphson Iteration
Decreasing feature sizes allow additional functionality to be added to future microprocessors to improve the performance of important application domains. As a result of rapid gro...
Liang-Kai Wang, Michael J. Schulte
ARITH
2003
IEEE
14 years 1 months ago
Representable Correcting Terms for Possibly Underflowing Floating Point Operations
Studying floating point arithmetic, authors have shown that the implemented operations (addition, subtraction, multiplication, division and square root) can compute a result and a...
Sylvie Boldo, Marc Daumas
VLSID
2006
IEEE
145views VLSI» more  VLSID 2006»
14 years 3 months ago
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel ...
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Sriniva...
ARITH
2011
IEEE
12 years 9 months ago
Fast Ripple-Carry Adders in Standard-Cell CMOS VLSI
— This paper presents a number of new high-radix ripple-carry adder designs based on Ling’s addition technique and a recently-published expansion thereof. The proposed adders a...
Neil Burgess
CIT
2006
Springer
14 years 1 months ago
Design of Novel Reversible Carry Look-Ahead BCD Subtractor
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard. A major enhancement to the standard is the addition of decimal format, thus the design of BCD arithmetic...
Himanshu Thapliyal, Sumedha K. Gupta