140 search results - page 17 / 28 » High-level design for asynchronous logic |
EDBT
2004
ACM
14 years 7 months ago
2004
ACM
T-Araneus is a tool for the generation of Web sites with special attention to temporal aspects. It builds on previous experiences in the management of data-intensive Web-sites, an...
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
In this paper, we propose a high-level variable selection for partial-scan approach to improve the testability of digital systems. The testability of a design is evaluated at the ...
ASYNC
1999
IEEE
13 years 12 months ago
1999
IEEE
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...
FUIN
2007
13 years 7 months ago
2007
Abstract. Josephs and Udding’s DI-Algebra offers a convenient way of specifying and verifying designs that must rely upon delay-insensitive signalling between modules (asynchrono...
MDM
2007
Springer
14 years 1 months ago
2007
Springer
Mobile phones are being increasingly equipped with sensors that ease retrieval of context information about a user. Context data can be aggregated with information centrally avail...