140 search results - page 5 / 28 » High-level design for asynchronous logic |
SBCCI
2006
ACM
14 years 1 months ago
2006
ACM
This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full...
ISMVL
2010
IEEE
14 years 21 days ago
2010
IEEE
—The purpose of secure devices such as smartcards is to protect secret information against software and hardware attacks. Implementation of the appropriate protection techniques ...
DATE
2003
IEEE
14 years 28 days ago
2003
IEEE
We present a visualization tool called PLFire, which allows a user to observe the behavior of a Phased Logic (PL) circuit. Phased logic is a technique for realizing self-timed cir...
ASYNC
1997
IEEE
13 years 12 months ago
1997
IEEE
The realisation of Delay-Insensitive (DI) asynchronous circuits with a CMOS ternary logic is described in this paper. The main advantage of temary logic is the easy realisation of...
FPGA
2004
ACM
14 years 1 months ago
2004
ACM
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...