140 search results - page 6 / 28 » High-level design for asynchronous logic |
ISMVL
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper shows how the application of a CMOS ternary logic is useful in the realisation of Delay Insensitive (01)asynchronous circuits. It is shown that fully DIasynchronous cir...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
TE
2010
13 years 2 months ago
2010
Abstract--As demand increases for circuits with higher performance, higher complexity, and decreased feature size, asynchronous (clockless) paradigms will become more widely used i...
ISLPED
2004
ACM
14 years 1 months ago
2004
ACM
In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low po...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
This paper presents a unifying framework for the modeling of asynchronous pipeline circuits. A pipeline protocol is captured in a graph-based model which defines the partial order...