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ICCAD
2001
IEEE
74views Hardware» more  ICCAD 2001»
14 years 6 months ago
Techniques for Including Dielectrics when Extracting Passive Low-Order Models of High Speed Interconnect
Interconnect structures including dielectrics can be modeled by an integral equation method using volume currents and surface charges for the conductors, and volume polarization c...
Luca Daniel, Alberto L. Sangiovanni-Vincentelli, J...
PATMOS
2005
Springer
14 years 3 months ago
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing
Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ pr...
Giorgos Dimitrakopoulos, Dimitris Nikolos
ISHPC
2003
Springer
14 years 3 months ago
Chordal Topologies for Interconnection Networks
Abstract. The class of dense circulant graphs of degree four with optimal distance-related properties is analyzed in this paper. An algebraic study of this class is done. Two geome...
Ramón Beivide, Carmen Martínez, Cruz...
DSD
2006
IEEE
126views Hardware» more  DSD 2006»
14 years 3 months ago
Off-Line Testing of Delay Faults in NoC Interconnects
Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when th...
Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimu...
VLSI
2010
Springer
13 years 8 months ago
Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs
—This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced ...
Fengda Sun, Alessandro Cevrero, Panagiotis Athanas...