72 search results - page 5 / 15 » High-throughput Pipelined Mergesort |
ASAP
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...
EUROPAR
2008
Springer
13 years 9 months ago
2008
Springer
Chip multiprocessors designed for streaming applications such as Cell BE offer impressive peak performance but suffer from limited bandwidth to offchip main memory. As the number o...
ISSS
1995
IEEE
13 years 11 months ago
1995
IEEE
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
FPT
2005
IEEE
14 years 1 months ago
2005
IEEE
Aggressive pipelining allows FPGAs to achieve high throughput on many Digital Signal Processing applications. However, cyclic data dependencies in the computation can limit pipeli...
DELTA
2010
IEEE
14 years 23 days ago
2010
IEEE
— FPGAs, (Field-Programmable Gate Arrays) are often used for embedded image processing applications. Parallelism, and in particular pipelining, is the most suitable architecture ...