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JUCS
2007
102views more  JUCS 2007»
13 years 7 months ago
The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation
: This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining ...
Oscar Pérez, Yves Berviller, Camel Tanougas...
INFOCOM
2008
IEEE
14 years 2 months ago
Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup
—Continuous growth in network link rates poses a strong demand on high speed IP lookup engines. While Ternary Content Addressable Memory (TCAM) based solutions serve most of toda...
Weirong Jiang, Qingbo Wang, Viktor K. Prasanna
IPPS
2008
IEEE
14 years 2 months ago
Parallel IP lookup using multiple SRAM-based pipelines
Pipelined SRAM-based algorithmic solutions have become competitive alternatives to TCAMs (ternary content addressable memories) for high throughput IP lookup. Multiple pipelines c...
Weirong Jiang, Viktor K. Prasanna
ISLPED
1995
ACM
134views Hardware» more  ISLPED 1995»
13 years 11 months ago
High-throughput and low-power DSP using clocked-CMOS circuitry
We argue that the clocked-CMOS (C2MOS) circuit family provides a very high throughput and low power alternative to other existing circuit techniques for the fast developing market...
Manjit Borah, Robert Michael Owens, Mary Jane Irwi...
BMCBI
2010
160views more  BMCBI 2010»
13 years 2 months ago
eHive: An Artificial Intelligence workflow system for genomic analysis
Background: The Ensembl project produces updates to its comparative genomics resources with each of its several releases per year. During each release cycle approximately two week...
Jessica Severin, Kathryn Beal, Albert J. Vilella, ...