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FPGA
2009
ACM
482views FPGA» more  FPGA 2009»
14 years 9 days ago
A 17ps time-to-digital converter implemented in 65nm FPGA technology
This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed archit...
Claudio Favi, Edoardo Charbon
BMCBI
2008
122views more  BMCBI 2008»
13 years 7 months ago
High-throughput bioinformatics with the Cyrille2 pipeline system
Background: Modern omics research involves the application of high-throughput technologies that generate vast volumes of data. These data need to be pre-processed, analyzed and in...
Mark W. E. J. Fiers, Ate van der Burgt, Erwin Date...
GLOBECOM
2009
IEEE
13 years 11 months ago
Energy-Efficient Multi-Pipeline Architecture for Terabit Packet Classification
Energy efficiency has become a critical concern in designing high speed packet classification engines for next generation routers. Although TCAM-based solutions can provide high th...
Weirong Jiang, Viktor K. Prasanna
ASPLOS
2004
ACM
14 years 1 months ago
Continual flow pipelines
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkar...
MTV
2007
IEEE
121views Hardware» more  MTV 2007»
14 years 1 months ago
Chico: An On-chip Hardware Checker for Pipeline Control Logic
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
Andrew DeOrio, Adam Bauserman, Valeria Bertacco