48 search results - page 7 / 10 » Highly pipelined asynchronous FPGAs |
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
FPL
2009
Springer
13 years 11 months ago
2009
Springer
The acceleration of molecular dynamics (MD) simulations using high performance reconfigurable computing (HPRC) has been much studied. Given the intense competition from multicore...
ICCD
1995
IEEE
13 years 11 months ago
1995
IEEE
We describe thedesign of a high performance asynchronous SCSI Small Computer Systems Interface controller data path and the associated control circuits. The data path is an asyn...
SPAA
1997
ACM
13 years 11 months ago
1997
ACM
Pipelining has been used in the design of many PRAM algorithms to reduce their asymptotic running time. Paul, Vishkin, and Wagener (PVW) used the approach in a parallel implementat...
HPCA
1998
IEEE
13 years 11 months ago
1998
IEEE
The counterflow pipeline concept was originated by Sproull et al.[1] to demonstrate the concept of asynchronous circuits. This architecture relies on distributed decision making an...