611 search results - page 119 / 123 » Highly scalable parallel sorting |
VLSID
2003
IEEE
2003
IEEE
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
14 years 7 months ago
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
IEEEPACT
2008
IEEE
14 years 1 months ago
2008
IEEE
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
VEE
2005
ACM
14 years 1 months ago
2005
ACM
Modern transactional response-time sensitive applications have run into practical limits on the size of garbage collected heaps. The heap can only grow until GC pauses exceed the ...
CONCUR
2005
Springer
14 years 1 months ago
2005
Springer
d Abstract) Vijay Saraswat1 and Radha Jagadeesan2 1 IBM T.J. Watson Research Lab 2 School of CTI, DePaul University Abstract. We present the concurrency and distribution primitives...