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DAC
2007
ACM
14 years 9 months ago
Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors
Three-Dimensional integration provides a simultaneous improvement in wire-related delay and power consumption of microprocessor circuits. Prior work has looked at the performance,...
Kiran Puttaswamy, Gabriel H. Loh
LSSC
2005
Springer
14 years 2 months ago
Systolic Architecture for Adaptive Censoring CFAR PI Detector
A new parallel algorithm for signal processing and a parallel systolic architecture of a robust constant false alarm rate (CFAR) processor with post-detection integration and adap...
Ivan Garvanov, Christo A. Kabakchiev, Plamen Daska...
CODES
2009
IEEE
13 years 9 months ago
A scalable parallel H.264 decoder on the cell broadband engine architecture
The H.264 video codec provides exceptional video compression while imposing dramatic increases in computational complexity over previous standards. While exploiting parallelism in...
Michael A. Baker, Pravin Dalale, Karam S. Chatha, ...
JCP
2008
162views more  JCP 2008»
13 years 8 months ago
A Hypercube-based Scalable Interconnection Network for Massively Parallel Computing
An important issues in the design of interconnection networks for massively parallel computers is scalability. A new scalable interconnection network topology, called Double-Loop H...
Youyao Liu, Jungang Han, Huimin Du
PADS
2003
ACM
14 years 1 months ago
Scalable RTI-Based Parallel Simulation of Networks
Federated simulation interfaces such as the High Level Architecture (HLA) were designed for interoperability, and as such are not traditionally associated with highperformance com...
Kalyan S. Perumalla, Alfred Park, Richard M. Fujim...