183 search results - page 27 / 37 » History-based memory mode prediction for improving memory pe... |
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
—A number of lifting-based video coding schemes have been recently proposed for scalable video coding. In this paper, we present a novel multi-view image codec based on a wavelet...
SBACPAD
2003
IEEE
14 years 20 days ago
2003
IEEE
Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ...
ECRTS
2009
IEEE
13 years 5 months ago
2009
IEEE
While hardware caches are generally effective at improving application performance, they greatly complicate performance prediction. Slight changes in memory layout or data access p...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
IPPS
2003
IEEE
14 years 21 days ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...