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» Hybrid cache architecture with disparate memory technologies
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HPCA
2002
IEEE
14 years 7 months ago
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T....
ISCA
1996
IEEE
103views Hardware» more  ISCA 1996»
13 years 11 months ago
Evaluation of Design Alternatives for a Multiprocessor Microprocessor
In the future, advanced integrated circuit processing and packaging technology will allow for several design options for multiprocessor microprocessors. In this paper we consider ...
Basem A. Nayfeh, Lance Hammond, Kunle Olukotun
WSC
1997
13 years 8 months ago
A Hybrid Tool for the Performance Evaluation of NUMA Architectures
We present a system for describing and solving closed queuing network models of the memory access performance of NUMA architectures. The system consists of a model description lan...
James Westall, Robert Geist
TVLSI
2008
150views more  TVLSI 2008»
13 years 6 months ago
Data Memory Subsystem Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
M. Bennaser, Yao Guo, Csaba Andras Moritz
CF
2010
ACM
13 years 7 months ago
Efficient cache design for solid-state drives
Solid-State Drives (SSDs) are data storage devices that use solid-state memory to store persistent data. Flash memory is the de facto nonvolatile technology used in most SSDs. It ...
Miaoqing Huang, Olivier Serres, Vikram K. Narayana...